1. Field of the Invention
The present invention relates, in general, to redundancy architecture for repairing semiconductor memories, and more particularly, to a redundancy architecture for improving a throughput of a test that includes repairing semiconductor memories.
2. Description of the Related Art
Redundancy is widely used in high-density semiconductor memories to improve product yield. As an example, a semiconductor memory may include redundant rows and columns, an address mapping circuit storing addresses of defective rows and columns, and a redundancy circuit for repairing defective rows and columns by redirecting the defective addresses to those of redundant rows and columns.
Defective addresses are often stored in fuses that are programmable by blowing them with laser beams. However, the use of the laser beams for programming the fuses requires blowing the fuses before packaging semiconductor memories into packages. This means that the semiconductor memories are not repairable after packaging, and thus the product yield is not effectively improved.
Use of programmable nonvolatile memories (NVRAMs) in place of the fuses effectively overcomes the drawback. Nonvolatile memories, including EPROMs (Electrically Programmable Read Only Memories), EEPROMS (Electrically Erasable Programmable Read Only Memories), allows defective addresses to be stored therein after packaging, and thus enables repairing semiconductor memories after packaging.
The use of a nonvolatile memory, however, increases a chip size of a semiconductor memory, because a nonvolatile memory requires a wider area per bit than a fuse circuitry.
A redundancy architecture for overcoming the aforementioned drawbacks is disclosed in Japanese Laid Open Patent Application (Jp-A 2002-25288), whose inventor is the same as the present invention. It should be noted that the aforementioned document was not yet disclosed one year before the priority date of this application, and thus the disclosed redundancy architecture should not be understood as a prior art.
FIG. 3 shows a synchronous dynamic random access memory (SDRAM) 10 including the disclosed redundancy architecture. The redundancy architecture is composed of both of a nonvolatile memory and a fuse circuit. The fuse circuit is programmed to store addresses of defective cells found before packaging the SDRAM 10, and the nonvolatile memory is programmed to store addresses of defective cells found after the packaging. Consequently, the redundancy architecture effectively avoids the chip size of the memory being increased.
In detail, the synchronous dynamic random access memory 10 is provided with a memory cell array 11, an address buffer 12, a command decoder 16, a mode register 17, a control logic circuit 18, a data input output circuit 19, a redundancy circuit 20 and a clock generator 21.
The memory cell array 11 is divided into banks <0> to <3> in which primary memory cells and redundant memory cells are arranged in rows and columns. The redundant memory cells are arranged in redundant columns 11a and redundant rows 11b. Each of the banks <0> to <3> includes a row address decoder 13, a column address decoder 14, and a sense amplifier 15.
The address buffer 12 receives bank address signals BA0 and BA1 and address signals A0 to A12 from an external circuit, such as a tester. The address buffer 12 demultiplexes the bank address signals BA0 and BA1 and the address signals A0 to A12 to identify a bank address, a row address and a column address.
The address signals A0 to A12 are also used for transferring a command instruction and a mode instruction. The command instruction is used for instructing the SDRAM 10 in the command, and the mode instruction is used for instructing the SDRAM 10 in an operation mode in which the SDRAM 10 is to be placed.
The row address decoder 13 receives and decodes the row address stored in the address buffer 12 to select rows associated with the row address.
The column address decoder 14 receives and decodes the column address to select a column associated with the column address.
The sense amplifier 15 identifies and outputs data store in the primary or redundant memory cells during a read operation, and also writes data into the memory cells during a write operation.
The command decoder 16 issues a command to control the SDRAM 10. The command decoder 16 receives control signals from an external circuit and the command instruction from the address buffer 12, and decodes the received control signals and command instruction to produce a command. The control signals includes a chip selection signal /CS indicative of whether the SDRAM 10 is selected, a row address strobe signal /RAS, a column address strobe signal /CAS, and a write enable signal /WE requesting a write operation. The slashes (“/”) at the heads of the numerals denoting the control signals represent that the control signals are activated when they have a “low” level, that is, they are set to logic 0.
The command provided by the command decoder 16 includes a read command that requests a read operation, a write command that requests a write operation, a mode register set command (MRS command) that request a rewrite of the mode register 17, a bank activate command (ACT command) that requests an activation of memory banks, a pre-charge command (PRE command) that requests for pre-charging bit lines of the memory cell array 11, and a non-operation command (NOR command).
The mode register 17 stores therein an operation mode in which the SDRAM 10 is placed. In response to an MRS command being issued, the mode register 17 determines an operation mode in which the SDRAM 10 is to be placed on the basis of the mode instruction received from the address buffer 12. The determined operation mode is rewritten into the mode register 17. The operation mode includes a test mode and a normal mode.
The control logic circuit 18 is responsive to the command issued by the command decoder 16 and the operation mode stored in the mode register 17 for generating inner control signals. The address buffer 12, the row decoder 13, the column decoder 14, the sense amplifier 15, the data input/output buffer 19, and the redundancy circuit 20 operate in response to the inner control signals.
The data input output circuit 19 transfers data between the sense amplifier 15 and the external circuit through data inputs/outputs DQ0 to DQ15. The data input output circuit 19 receives read data from the memory cell array 11 through the sense amplifier 15 and outputs the read data to an external circuit. The data input output circuit 19 also receives write data inputted from an external circuit and outputs the write data to the sense amplifier 15. The data input output circuit 19 is responsive to a control signal DQM provided from an external circuit to selectively output the write data through the through the input/output terminal DQ0 to DQ15.
The clock generator 21 receives an external clock signal CLK and a clock enable signal CKE to generate an internal clock signal. The circuits implemented within the SDRAM 10 operate in synchronization with the generated internal clock signal.
The redundancy circuit 20 includes first and second defective address mapping and compare circuit 20A and 20B.
The first defective address mapping and compare circuit 20A includes a nonvolatile memory (NVRAM) storing defective addresses, and a first address compare circuit comparing received address to the defective addresses. The NVRAM may include an EPROM or an EEPROM. The address compare circuit compares the address received from the address buffer 12 to the defective addresses stored in the nonvolatile memory.
The second defective address mapping and compare circuit 20B includes a fuse circuit and a second address compare circuit (both not shown). The fuse circuit includes fuses storing other defective addresses. The second address compare circuit compares the received address to the defective addresses stored in the fuse circuit.
When the received address matches one of the defective addresses, the control logic circuit 18 controls the row decoder 13 and the column decoder 14 to activate the redundant rows and columns.
The defective addresses of the defective cells found before packaging the SDRAM 10 are stored in the fuse circuit of the second defective address mapping and compare circuit 20B. When a defective cell is found by the test before packaging, the fuse circuit is programmed by blowing the fuses with laser beams to store the address of the defective cell.
On the other hand, the defective addresses of the defective cells found after the packaging are stored in the nonvolatile memory of the first defective address mapping and compare circuit 20A. Programming the nonvolatile memory is achieved by providing and writing data representative of the defective addresses.
The use of both the fuse circuit and the nonvolatile memory enables repairing the SDRAM 10 after the packaging while reducing the chip size of the SDRAM 10.
FIG. 1 shows a conventional process for repairing a semiconductor memory after packaging. The conventional repairing process exemplary includes the steps of testing functions of the semiconductor memory, using a tester 51 as described below with respect to FIG. 2, producing a mapping from defective addresses to redundancy rows or columns, and programming the nonvolatile memory.
With reference to FIG. 2, semiconductor memories 52 are generally tested and repaired using a tester 51 that may be connected to a personal computer 53. The tester 51 includes a comparator and a fail bit memory (FBM, not shown) and operates on the basis of EWS software. The testing of the functions begins with providing the memory chips 52 respectively including semiconductor memories with test patterns by the tester 51. The memory chips are tested one at a time so that a first memory chip 52 is “ON TEST” and the remaining memory chips 52 are “WAITING” to be tested. The test patterns include test addresses and test data. The tester 51 then receives read data from the semiconductor memories and compares the received read data to anticipated data by the comparator to produce pass/fail data representative of defective cells. The pass/fail data is stored in the fail bit memory.
When a defective cell is found during the function test, the tester 51 produces a mapping from the defective address(es) to the redundancy row(s) or column(s). The tester 51 then places the defective semiconductor memory in a test mode to allow the nonvolatile memory to be programmed. Then, the tester 51 programs the nonvolatile memory to store the defective address(es).
A drawback of the conventional repairing process is that considerable costs are required for testing and repairing many semiconductor memories concurrently. To test and repair a plurality of semiconductor memories in parallel, the same number of expensive comparators and expensive fail bit memories are required. Thus, the increase of the semiconductor memories tested and repaired in parallel requires testers to be increased in the number thereof, or to be implemented with many comparators and fail bit memories. Consequently, the parallel testing and repairing drives up the costs.
Another drawback of the conventional repairing process is that it increases a throughput of the testing and repairing because the data transfer between the tester and the semiconductor memory causes considerable delays. The conventional repairing process requires that the tester 51 and the memory chip 52 exchange large data. The data to be exchanged typically includes write data to be written in the memory cell array 10, test addresses, a command, read data from the memory cell array 10, defective addresses to be stored in the NVRAM the first defective address mapping and-compare circuit 20A, and a test command to allow the NVRAM to be programmed. Exchanging large data increases the throughput of testing and repairing the memory chip 52, and thus is undesirable, because the increase in the throughput considerably raises the cost of the semiconductor memory.
A need exists to provide a redundancy architecture for improving the throughput of testing and repairing the semiconductor memory with a redundancy architecture after packaging, and simultaneously reducing the chip size thereof.